{"day":"26","type":"conference","file":[{"content_type":"application/pdf","file_name":"2018_LNCS_Elgyuett.pdf","access_level":"open_access","creator":"dernst","relation":"main_file","checksum":"e5d81c9b50a6bd9d8a2c16953aad7e23","file_id":"8638","success":1,"date_created":"2020-10-09T06:24:21Z","file_size":537219,"date_updated":"2020-10-09T06:24:21Z"}],"date_updated":"2023-09-13T08:58:34Z","article_processing_charge":"No","month":"08","publication_status":"published","date_published":"2018-08-26T00:00:00Z","abstract":[{"text":"We solve the offline monitoring problem for timed propositional temporal logic (TPTL), interpreted over dense-time Boolean signals. The variant of TPTL we consider extends linear temporal logic (LTL) with clock variables and reset quantifiers, providing a mechanism to specify real-time constraints. We first describe a general monitoring algorithm based on an exhaustive computation of the set of satisfying clock assignments as a finite union of zones. We then propose a specialized monitoring algorithm for the one-variable case using a partition of the time domain based on the notion of region equivalence, whose complexity is linear in the length of the signal, thereby generalizing a known result regarding the monitoring of metric temporal logic (MTL). The region and zone representations of time constraints are known from timed automata verification and can also be used in the discrete-time case. Our prototype implementation appears to outperform previous discrete-time implementations of TPTL monitoring,","lang":"eng"}],"department":[{"_id":"ToHe"}],"date_created":"2018-12-11T11:44:31Z","user_id":"c635000d-4b10-11ee-a964-aac5a93f6ac1","oa_version":"Submitted Version","oa":1,"scopus_import":"1","publisher":"Springer","status":"public","title":"Monitoring temporal logic with clock variables","quality_controlled":"1","alternative_title":["LNCS"],"author":[{"last_name":"Elgyütt","first_name":"Adrian","id":"4A2E9DBA-F248-11E8-B48F-1D18A9856A87","full_name":"Elgyütt, Adrian"},{"id":"40960E6E-F248-11E8-B48F-1D18A9856A87","full_name":"Ferrere, Thomas","first_name":"Thomas","last_name":"Ferrere","orcid":"0000-0001-5199-3143"},{"id":"40876CD8-F248-11E8-B48F-1D18A9856A87","full_name":"Henzinger, Thomas A","last_name":"Henzinger","first_name":"Thomas A","orcid":"0000−0002−2985−7724"}],"has_accepted_license":"1","page":"53 - 70","doi":"10.1007/978-3-030-00151-3_4","external_id":{"isi":["000884993200004"]},"conference":{"name":"FORMATS: Formal Modeling and Analysis of Timed Systems","start_date":"2018-09-04","location":"Beijing, China","end_date":"2018-09-06"},"citation":{"short":"A. Elgyütt, T. Ferrere, T.A. Henzinger, in:, Springer, 2018, pp. 53–70.","ama":"Elgyütt A, Ferrere T, Henzinger TA. Monitoring temporal logic with clock variables. In: Vol 11022. Springer; 2018:53-70. doi:<a href=\"https://doi.org/10.1007/978-3-030-00151-3_4\">10.1007/978-3-030-00151-3_4</a>","chicago":"Elgyütt, Adrian, Thomas Ferrere, and Thomas A Henzinger. “Monitoring Temporal Logic with Clock Variables,” 11022:53–70. Springer, 2018. <a href=\"https://doi.org/10.1007/978-3-030-00151-3_4\">https://doi.org/10.1007/978-3-030-00151-3_4</a>.","apa":"Elgyütt, A., Ferrere, T., &#38; Henzinger, T. A. (2018). Monitoring temporal logic with clock variables (Vol. 11022, pp. 53–70). Presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China: Springer. <a href=\"https://doi.org/10.1007/978-3-030-00151-3_4\">https://doi.org/10.1007/978-3-030-00151-3_4</a>","ista":"Elgyütt A, Ferrere T, Henzinger TA. 2018. Monitoring temporal logic with clock variables. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022, 53–70.","ieee":"A. Elgyütt, T. Ferrere, and T. A. Henzinger, “Monitoring temporal logic with clock variables,” presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China, 2018, vol. 11022, pp. 53–70.","mla":"Elgyütt, Adrian, et al. <i>Monitoring Temporal Logic with Clock Variables</i>. Vol. 11022, Springer, 2018, pp. 53–70, doi:<a href=\"https://doi.org/10.1007/978-3-030-00151-3_4\">10.1007/978-3-030-00151-3_4</a>."},"_id":"81","language":[{"iso":"eng"}],"volume":11022,"publist_id":"7973","intvolume":"     11022","year":"2018","isi":1,"file_date_updated":"2020-10-09T06:24:21Z","project":[{"grant_number":"S11402-N23","_id":"25F5A88A-B435-11E9-9278-68D0E5697425","name":"Moderne Concurrency Paradigms","call_identifier":"FWF"},{"call_identifier":"FWF","grant_number":"Z211","name":"The Wittgenstein Prize","_id":"25F42A32-B435-11E9-9278-68D0E5697425"}],"ddc":["000"]}