{"month":"04","author":[{"orcid":"0000-0001-5199-3143","first_name":"Thomas","last_name":"Ferrere","id":"40960E6E-F248-11E8-B48F-1D18A9856A87","full_name":"Ferrere, Thomas"},{"full_name":"Nickovic, Dejan","id":"41BCEE5C-F248-11E8-B48F-1D18A9856A87","first_name":"Dejan","last_name":"Nickovic"},{"full_name":"Donzé, Alexandre","last_name":"Donzé","first_name":"Alexandre"},{"full_name":"Ito, Hisahiro","last_name":"Ito","first_name":"Hisahiro"},{"first_name":"James","last_name":"Kapinski","full_name":"Kapinski, James"}],"citation":{"ama":"Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. Interface-aware signal temporal logic. In: <i>Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control</i>. ACM; 2019:57-66. doi:<a href=\"https://doi.org/10.1145/3302504.3311800\">10.1145/3302504.3311800</a>","chicago":"Ferrere, Thomas, Dejan Nickovic, Alexandre Donzé, Hisahiro Ito, and James Kapinski. “Interface-Aware Signal Temporal Logic.” In <i>Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control</i>, 57–66. ACM, 2019. <a href=\"https://doi.org/10.1145/3302504.3311800\">https://doi.org/10.1145/3302504.3311800</a>.","mla":"Ferrere, Thomas, et al. “Interface-Aware Signal Temporal Logic.” <i>Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control</i>, ACM, 2019, pp. 57–66, doi:<a href=\"https://doi.org/10.1145/3302504.3311800\">10.1145/3302504.3311800</a>.","apa":"Ferrere, T., Nickovic, D., Donzé, A., Ito, H., &#38; Kapinski, J. (2019). Interface-aware signal temporal logic. In <i>Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control</i> (pp. 57–66). Montreal, Canada: ACM. <a href=\"https://doi.org/10.1145/3302504.3311800\">https://doi.org/10.1145/3302504.3311800</a>","ieee":"T. Ferrere, D. Nickovic, A. Donzé, H. Ito, and J. Kapinski, “Interface-aware signal temporal logic,” in <i>Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control</i>, Montreal, Canada, 2019, pp. 57–66.","ista":"Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. 2019. Interface-aware signal temporal logic. Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control. HSCC: Hybrid Systems Computation and Control, 57–66.","short":"T. Ferrere, D. Nickovic, A. Donzé, H. Ito, J. Kapinski, in:, Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control, ACM, 2019, pp. 57–66."},"title":"Interface-aware signal temporal logic","project":[{"_id":"25832EC2-B435-11E9-9278-68D0E5697425","name":"Rigorous Systems Engineering","grant_number":"S 11407_N23","call_identifier":"FWF"},{"name":"The Wittgenstein Prize","call_identifier":"FWF","grant_number":"Z211","_id":"25F42A32-B435-11E9-9278-68D0E5697425"}],"date_published":"2019-04-16T00:00:00Z","file_date_updated":"2020-10-08T17:25:45Z","date_created":"2019-05-13T08:13:46Z","scopus_import":"1","department":[{"_id":"ToHe"}],"type":"conference","article_processing_charge":"No","ddc":["000"],"status":"public","_id":"6428","file":[{"access_level":"open_access","checksum":"b8e967081e051d1c55ca5d18fb187890","file_name":"2019_ACM_Ferrere.pdf","creator":"dernst","content_type":"application/pdf","success":1,"date_updated":"2020-10-08T17:25:45Z","date_created":"2020-10-08T17:25:45Z","file_id":"8633","file_size":1055421,"relation":"main_file"}],"quality_controlled":"1","publication_status":"published","abstract":[{"lang":"eng","text":"Safety and security are major concerns in the development of Cyber-Physical Systems (CPS). Signal temporal logic (STL) was proposedas a language to specify and monitor the correctness of CPS relativeto formalized requirements. Incorporating STL into a developmentprocess enables designers to automatically monitor and diagnosetraces, compute robustness estimates based on requirements, andperform requirement falsification, leading to productivity gains inverification and validation activities; however, in its current formSTL is agnostic to the input/output classification of signals, andthis negatively impacts the relevance of the analysis results.In this paper we propose to make the interface explicit in theSTL language by introducing input/output signal declarations. Wethen define new measures of input vacuity and output robustnessthat better reflect the nature of the system and the specification in-tent. The resulting framework, which we call interface-aware signaltemporal logic (IA-STL), aids verification and validation activities.We demonstrate the benefits of IA-STL on several CPS analysisactivities: (1) robustness-driven sensitivity analysis, (2) falsificationand (3) fault localization. We describe an implementation of our en-hancement to STL and associated notions of robustness and vacuityin a prototype extension of Breach, a MATLAB®/Simulink®toolboxfor CPS verification and validation. We explore these methodologi-cal improvements and evaluate our results on two examples fromthe automotive domain: a benchmark powertrain control systemand a hydrogen fuel cell system."}],"publisher":"ACM","user_id":"4359f0d1-fa6c-11eb-b949-802e58b17ae8","has_accepted_license":"1","external_id":{"isi":["000516713900007"]},"oa":1,"oa_version":"Submitted Version","page":"57-66","isi":1,"conference":{"start_date":"2019-04-16","name":"HSCC: Hybrid Systems Computation and Control","location":"Montreal, Canada","end_date":"2019-04-18"},"publication":"Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control","doi":"10.1145/3302504.3311800","day":"16","date_updated":"2023-08-25T10:19:23Z","year":"2019","language":[{"iso":"eng"}],"publication_identifier":{"isbn":["9781450362825"]}}