{"conference":{"name":"CAV: Computer Aided Verification","start_date":"1997-06-22","end_date":"1997-06-25","location":"Haifa, Israel"},"citation":{"short":"R. Alur, R. Brayton, T.A. Henzinger, S. Qadeer, S. Rajamani, in:, 9th International Conference on Computer Aided Verification, Springer, 1997, pp. 340–351.","ama":"Alur R, Brayton R, Henzinger TA, Qadeer S, Rajamani S. Partial-order reduction in symbolic state-space exploration. In: <i>9th International Conference on Computer Aided Verification</i>. Vol 1254. Springer; 1997:340-351. doi:<a href=\"https://doi.org/10.1007/3-540-63166-6_34\">10.1007/3-540-63166-6_34</a>","ista":"Alur R, Brayton R, Henzinger TA, Qadeer S, Rajamani S. 1997. Partial-order reduction in symbolic state-space exploration. 9th International Conference on Computer Aided Verification. CAV: Computer Aided Verification, LNCS, vol. 1254, 340–351.","apa":"Alur, R., Brayton, R., Henzinger, T. A., Qadeer, S., &#38; Rajamani, S. (1997). Partial-order reduction in symbolic state-space exploration. In <i>9th International Conference on Computer Aided Verification</i> (Vol. 1254, pp. 340–351). Haifa, Israel: Springer. <a href=\"https://doi.org/10.1007/3-540-63166-6_34\">https://doi.org/10.1007/3-540-63166-6_34</a>","chicago":"Alur, Rajeev, Robert Brayton, Thomas A Henzinger, Shaz Qadeer, and Sriram Rajamani. “Partial-Order Reduction in Symbolic State-Space Exploration.” In <i>9th International Conference on Computer Aided Verification</i>, 1254:340–51. Springer, 1997. <a href=\"https://doi.org/10.1007/3-540-63166-6_34\">https://doi.org/10.1007/3-540-63166-6_34</a>.","ieee":"R. Alur, R. Brayton, T. A. Henzinger, S. Qadeer, and S. Rajamani, “Partial-order reduction in symbolic state-space exploration,” in <i>9th International Conference on Computer Aided Verification</i>, Haifa, Israel, 1997, vol. 1254, pp. 340–351.","mla":"Alur, Rajeev, et al. “Partial-Order Reduction in Symbolic State-Space Exploration.” <i>9th International Conference on Computer Aided Verification</i>, vol. 1254, Springer, 1997, pp. 340–51, doi:<a href=\"https://doi.org/10.1007/3-540-63166-6_34\">10.1007/3-540-63166-6_34</a>."},"language":[{"iso":"eng"}],"_id":"4608","doi":"10.1007/3-540-63166-6_34","page":"340 - 351","author":[{"first_name":"Rajeev","last_name":"Alur","full_name":"Alur, Rajeev"},{"full_name":"Brayton, Robert","first_name":"Robert","last_name":"Brayton"},{"orcid":"0000−0002−2985−7724","full_name":"Henzinger, Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","last_name":"Henzinger"},{"full_name":"Qadeer, Shaz","first_name":"Shaz","last_name":"Qadeer"},{"full_name":"Rajamani, Sriram","last_name":"Rajamani","first_name":"Sriram"}],"publication":"9th International Conference on Computer Aided Verification","publication_identifier":{"isbn":["9783540631668"]},"acknowledgement":"This research was supported in part by the ONR YIP award N00014-95-1-0520, by the NSF CAREER award CCR-9501708, by the NSF grant CCR-9504469, by the AFOSR contract F49620-93-1-0056, by the ARO MURI grant DAAH-04-96-1-0341, by the ARPA grant NAG2-892, and by the Semiconductor Research Corporation contracts DC-324.036 and DC-324.005.","intvolume":"      1254","publist_id":"99","volume":1254,"year":"1997","publication_status":"published","date_published":"1997-01-01T00:00:00Z","extern":"1","abstract":[{"text":"State space explosion is a fundamental obstacle in formal verification of designs and protocols. Several techniques for combating this problem have emerged in the past few years, among which two are significant: partial-order reductions and symbolic state space search. In asynchronous systems, interleavings of independent concurrent events are equivalent, and only a representative interleaving needs to be explored to verify local properties. Partial-order methods exploit this redundancy and visit only a subset of the reachable states. Symbolic techniques, on the other hand, capture the transition relation of a system and the set of reachable states as boolean functions. In many cases, these functions can be represented compactly using binary decision diagrams (BDDs). Traditionally, the two techniques have been practiced by two different schools—partial-order methods with enumerative depth-first search for the analysis of asynchronous network protocols, and symbolic breadth-first search for the analysis of synchronous hardware designs. We combine both approaches and develop a method for using partial-order reduction techniques in symbolic BDD-based invariant checking. We present theoretical results to prove the correctness of the method, and experimental results to demonstrate its efficacy.","lang":"eng"}],"type":"conference","day":"01","month":"01","article_processing_charge":"No","date_updated":"2022-08-16T14:09:54Z","quality_controlled":"1","title":"Partial-order reduction in symbolic state-space exploration","status":"public","alternative_title":["LNCS"],"oa_version":"None","date_created":"2018-12-11T12:09:44Z","user_id":"ea97e931-d5af-11eb-85d4-e6957dddbf17","publisher":"Springer","scopus_import":"1"}