{"date_published":"2003-12-01T00:00:00Z","user_id":"2DF688A6-F248-11E8-B48F-1D18A9856A87","page":"1 - 201","year":"2003","status":"public","publisher":"University of California, Berkeley","day":"01","citation":{"apa":"Majumdar, R. (2003). <i>Symbolic algorithms for verification and control</i>. University of California, Berkeley.","chicago":"Majumdar, Ritankar. “Symbolic Algorithms for Verification and Control.” University of California, Berkeley, 2003.","ista":"Majumdar R. 2003. Symbolic algorithms for verification and control. University of California, Berkeley.","ieee":"R. Majumdar, “Symbolic algorithms for verification and control,” University of California, Berkeley, 2003.","ama":"Majumdar R. Symbolic algorithms for verification and control. 2003:1-201.","mla":"Majumdar, Ritankar. <i>Symbolic Algorithms for Verification and Control</i>. University of California, Berkeley, 2003, pp. 1–201.","short":"R. Majumdar, Symbolic Algorithms for Verification and Control, University of California, Berkeley, 2003."},"date_created":"2018-12-11T12:08:44Z","month":"12","article_processing_charge":"No","publication_status":"published","abstract":[{"lang":"eng","text":"Methods for the formal specification and verification of systems are indispensible for the development of complex yet correct systems. In formal verification, the designer describes the system in a modeling language with a well-defined semantics, and this system description is analyzed against a set of correctness requirements. Model checking is an algorithmic technique to check that a system description indeed satisfies correctness requirements given as logical specifications. While successful in hardware verification, the potential for model checking for software and embedded systems has not yet been realized. This is because traditional model checking focuses on systems modeled as finite state-transition graphs. While a natural model for hardware (especially synchronous hardware), state-transition graphs often do not capture software and embedded systems at an appropriate level of granularity. This dissertation considers two orthogonal extensions to finite state-transition graphs making model checking techniques applicable to both a wider class of systems and a wider class of properties.\r\n\r\nThe first direction is an extension to infinite-state structures finitely represented using constraints and operations on constraints. Infinite state arises when we wish to model variables with unbounded range (e.g., integers), or data structures, or real time. We provide a uniform framework of symbolic region algebras to study model checking of infinite-state systems. We also provide sufficient language-independent termination conditions for symbolic model checking algorithms on infinite state systems.\r\n\r\nThe second direction supplements verification with game theoretic reasoning. Games are natural models for interactions between components. We study game theoretic behavior with winning conditions given by temporal logic objectives both in the deterministic and in the probabilistic context. For deterministic games, we provide an extremal model characterization of fixpoint algorithms that link solutions of verification problems to solutions for games. For probabilistic games we study fixpoint characterization of winning probabilities for games with omega-regular winning objectives, and construct (epsilon-)optimal winning strategies."}],"oa_version":"None","author":[{"last_name":"Majumdar","full_name":"Majumdar, Ritankar","first_name":"Ritankar"}],"_id":"4416","title":"Symbolic algorithms for verification and control","language":[{"iso":"eng"}],"supervisor":[{"id":"40876CD8-F248-11E8-B48F-1D18A9856A87","last_name":"Henzinger","orcid":"0000-0002-2985-7724","first_name":"Thomas A","full_name":"Henzinger, Thomas A"}],"publist_id":"313","date_updated":"2021-01-12T07:56:49Z","type":"dissertation","extern":"1"}