{"user_id":"4435EBFC-F248-11E8-B48F-1D18A9856A87","publist_id":"3256","date_created":"2018-12-11T12:02:53Z","oa_version":"None","publisher":"ACM","year":"2011","acknowledgement":"This work was partially supported by the ERC Advanced Grant QUAREM, the FWF NFN Grant S11402-N23 (RiSE), and the EU NOE Grant ArtistDesign.","status":"public","quality_controlled":"1","title":"From boolean to quantitative synthesis","project":[{"call_identifier":"FP7","grant_number":"267989","name":"Quantitative Reactive Modeling","_id":"25EE3708-B435-11E9-9278-68D0E5697425"},{"_id":"25F5A88A-B435-11E9-9278-68D0E5697425","name":"Moderne Concurrency Paradigms","grant_number":"S11402-N23","call_identifier":"FWF"},{"grant_number":"214373","name":"Design for Embedded Systems","_id":"25F1337C-B435-11E9-9278-68D0E5697425","call_identifier":"FP7"}],"doi":"10.1145/2038642.2038666","page":"149 - 154","author":[{"full_name":"Cerny, Pavol","id":"4DCBEFFE-F248-11E8-B48F-1D18A9856A87","last_name":"Cerny","first_name":"Pavol"},{"orcid":"0000−0002−2985−7724","full_name":"Henzinger, Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","last_name":"Henzinger","first_name":"Thomas A"}],"day":"09","type":"conference","date_updated":"2021-01-12T07:42:55Z","month":"10","ec_funded":1,"conference":{"start_date":"2011-10-09","name":"EMSOFT: Embedded Software ","end_date":"2011-10-14","location":"Taipei; Taiwan"},"publication_status":"published","date_published":"2011-10-09T00:00:00Z","citation":{"ieee":"P. Cerny and T. A. Henzinger, “From boolean to quantitative synthesis,” presented at the EMSOFT: Embedded Software , Taipei; Taiwan, 2011, pp. 149–154.","mla":"Cerny, Pavol, and Thomas A. Henzinger. <i>From Boolean to Quantitative Synthesis</i>. ACM, 2011, pp. 149–54, doi:<a href=\"https://doi.org/10.1145/2038642.2038666\">10.1145/2038642.2038666</a>.","short":"P. Cerny, T.A. Henzinger, in:, ACM, 2011, pp. 149–154.","ama":"Cerny P, Henzinger TA. From boolean to quantitative synthesis. In: ACM; 2011:149-154. doi:<a href=\"https://doi.org/10.1145/2038642.2038666\">10.1145/2038642.2038666</a>","ista":"Cerny P, Henzinger TA. 2011. From boolean to quantitative synthesis. EMSOFT: Embedded Software , 149–154.","apa":"Cerny, P., &#38; Henzinger, T. A. (2011). From boolean to quantitative synthesis (pp. 149–154). Presented at the EMSOFT: Embedded Software , Taipei; Taiwan: ACM. <a href=\"https://doi.org/10.1145/2038642.2038666\">https://doi.org/10.1145/2038642.2038666</a>","chicago":"Cerny, Pavol, and Thomas A Henzinger. “From Boolean to Quantitative Synthesis,” 149–54. ACM, 2011. <a href=\"https://doi.org/10.1145/2038642.2038666\">https://doi.org/10.1145/2038642.2038666</a>."},"abstract":[{"text":"Motivated by improvements in constraint-solving technology and by the increase of routinely available computational power, partial-program synthesis is emerging as an effective approach for increasing programmer productivity. The goal of the approach is to allow the programmer to specify a part of her intent imperatively (that is, give a partial program) and a part of her intent declaratively, by specifying which conditions need to be achieved or maintained. The task of the synthesizer is to construct a program that satisfies the specification. As an example, consider a partial program where threads access shared data without using any synchronization mechanism, and a declarative specification that excludes data races and deadlocks. The task of the synthesizer is then to place locks into the program code in order for the program to meet the specification.\r\n\r\nIn this paper, we argue that quantitative objectives are needed in partial-program synthesis in order to produce higher-quality programs, while enabling simpler specifications. Returning to the example, the synthesizer could construct a naive solution that uses one global lock for shared data. This can be prevented either by constraining the solution space further (which is error-prone and partly defeats the point of synthesis), or by optimizing a quantitative objective that models performance. Other quantitative notions useful in synthesis include fault tolerance, robustness, resource (memory, power) consumption, and information flow.","lang":"eng"}],"department":[{"_id":"ToHe"}],"language":[{"iso":"eng"}],"_id":"3359"}