[{"main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/model_checking_transactional_memories.pdf"}],"doi":"10.1145/1375581.1375626","publication_status":"published","abstract":[{"lang":"eng","text":"Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memory. We show that, under certain conditions, the verification problem can be reduced to a finite-state problem, and we illustrate the use of the method by proving the correctness of several STMs, including two-phase locking, DSTM, TL2, and optimistic concurrency control. The safety properties we consider include strict serializability and opacity; the liveness properties include obstruction freedom, livelock freedom, and wait freedom.\n\nOur main contribution lies in the structure of the proofs, which are largely automated and not restricted to the STMs mentioned above. In a first step we show that every STM that enjoys certain structural properties either violates a safety or liveness requirement on some program with two threads and two shared variables, or satisfies the requirement on all programs. In the second step we use a model checker to prove the requirement for the STM applied to a most general program with two threads and two variables. In the safety case, the model checker constructs a simulation relation between two carefully constructed finite-state transition systems, one representing the given STM applied to a most general program, and the other representing a most liberal safe STM applied to the same program. In the liveness case, the model checker analyzes fairness conditions on the given STM transition system."}],"file_date_updated":"2020-07-14T12:46:28Z","type":"conference","extern":1,"citation":{"mla":"Guerraoui, Rachid, et al. <i>Model Checking Transactional Memories</i>. ACM, 2008, pp. 372–82, doi:<a href=\"https://doi.org/10.1145/1375581.1375626\">10.1145/1375581.1375626</a>.","apa":"Guerraoui, R., Henzinger, T. A., Jobstmann, B., &#38; Singh, V. (2008). Model checking transactional memories (pp. 372–382). Presented at the PLDI: Programming Languages Design and Implementation, ACM. <a href=\"https://doi.org/10.1145/1375581.1375626\">https://doi.org/10.1145/1375581.1375626</a>","chicago":"Guerraoui, Rachid, Thomas A Henzinger, Barbara Jobstmann, and Vasu Singh. “Model Checking Transactional Memories,” 372–82. ACM, 2008. <a href=\"https://doi.org/10.1145/1375581.1375626\">https://doi.org/10.1145/1375581.1375626</a>.","ista":"Guerraoui R, Henzinger TA, Jobstmann B, Singh V. 2008. Model checking transactional memories. PLDI: Programming Languages Design and Implementation, 372–382.","short":"R. Guerraoui, T.A. Henzinger, B. Jobstmann, V. Singh, in:, ACM, 2008, pp. 372–382.","ieee":"R. Guerraoui, T. A. Henzinger, B. Jobstmann, and V. Singh, “Model checking transactional memories,” presented at the PLDI: Programming Languages Design and Implementation, 2008, pp. 372–382.","ama":"Guerraoui R, Henzinger TA, Jobstmann B, Singh V. Model checking transactional memories. In: ACM; 2008:372-382. doi:<a href=\"https://doi.org/10.1145/1375581.1375626\">10.1145/1375581.1375626</a>"},"day":"01","quality_controlled":0,"status":"public","_id":"4384","date_created":"2018-12-11T12:08:34Z","conference":{"name":"PLDI: Programming Languages Design and Implementation"},"publist_id":"1073","page":"372 - 382","year":"2008","publisher":"ACM","date_published":"2008-01-01T00:00:00Z","month":"01","title":"Model checking transactional memories","author":[{"full_name":"Guerraoui, Rachid","first_name":"Rachid","last_name":"Guerraoui"},{"full_name":"Thomas Henzinger","last_name":"Henzinger","orcid":"0000−0002−2985−7724","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A"},{"full_name":"Jobstmann, Barbara","last_name":"Jobstmann","first_name":"Barbara"},{"full_name":"Vasu Singh","id":"4DAE2708-F248-11E8-B48F-1D18A9856A87","first_name":"Vasu","last_name":"Singh"}],"oa":1,"file":[{"date_updated":"2020-07-14T12:46:28Z","date_created":"2018-12-12T10:14:05Z","file_name":"IST-2012-74-v1+1_Model_checking_transactional_memories.pdf","checksum":"1238258a27f212fc1a2050a9a246da20","access_level":"open_access","relation":"main_file","content_type":"application/pdf","file_id":"5054","creator":"system","file_size":201583}],"date_updated":"2021-01-12T07:56:34Z"},{"date_updated":"2021-01-12T07:56:35Z","title":"Permissiveness in transactional memories","author":[{"full_name":"Guerraoui, Rachid","first_name":"Rachid","last_name":"Guerraoui"},{"orcid":"0000−0002−2985−7724","last_name":"Henzinger","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","full_name":"Thomas Henzinger"},{"full_name":"Vasu Singh","last_name":"Singh","first_name":"Vasu","id":"4DAE2708-F248-11E8-B48F-1D18A9856A87"}],"intvolume":"      5218","month":"09","alternative_title":["LNCS"],"date_published":"2008-09-10T00:00:00Z","acknowledgement":"This research was supported by the Swiss National Science Foundation.","publisher":"Springer","year":"2008","page":"305 - 319","conference":{"name":"DISC: Distributed Computing"},"publist_id":"1072","date_created":"2018-12-11T12:08:35Z","_id":"4386","quality_controlled":0,"status":"public","day":"10","extern":1,"citation":{"short":"R. Guerraoui, T.A. Henzinger, V. Singh, in:, Springer, 2008, pp. 305–319.","ieee":"R. Guerraoui, T. A. Henzinger, and V. Singh, “Permissiveness in transactional memories,” presented at the DISC: Distributed Computing, 2008, vol. 5218, pp. 305–319.","ista":"Guerraoui R, Henzinger TA, Singh V. 2008. Permissiveness in transactional memories. DISC: Distributed Computing, LNCS, vol. 5218, 305–319.","ama":"Guerraoui R, Henzinger TA, Singh V. Permissiveness in transactional memories. In: Vol 5218. Springer; 2008:305-319. doi:<a href=\"https://doi.org/10.1007/978-3-540-87779-0_21\">10.1007/978-3-540-87779-0_21</a>","chicago":"Guerraoui, Rachid, Thomas A Henzinger, and Vasu Singh. “Permissiveness in Transactional Memories,” 5218:305–19. Springer, 2008. <a href=\"https://doi.org/10.1007/978-3-540-87779-0_21\">https://doi.org/10.1007/978-3-540-87779-0_21</a>.","apa":"Guerraoui, R., Henzinger, T. A., &#38; Singh, V. (2008). Permissiveness in transactional memories (Vol. 5218, pp. 305–319). Presented at the DISC: Distributed Computing, Springer. <a href=\"https://doi.org/10.1007/978-3-540-87779-0_21\">https://doi.org/10.1007/978-3-540-87779-0_21</a>","mla":"Guerraoui, Rachid, et al. <i>Permissiveness in Transactional Memories</i>. Vol. 5218, Springer, 2008, pp. 305–19, doi:<a href=\"https://doi.org/10.1007/978-3-540-87779-0_21\">10.1007/978-3-540-87779-0_21</a>."},"volume":5218,"type":"conference","abstract":[{"lang":"eng","text":"We introduce the notion of permissiveness in transactional memories (TM). Intuitively, a TM is permissive if it never aborts a transaction when it need not. More specifically, a TM is permissive with respect to a safety property p if the TM accepts every history that satisfies p. Permissiveness, like safety and liveness, can be used as a metric to compare TMs. We illustrate that it is impractical to achieve permissiveness deterministically, and then show how randomization can be used to achieve permissiveness efficiently. We introduce Adaptive Validation STM (AVSTM), which is probabilistically permissive with respect to opacity; that is, every opaque history is accepted by AVSTM with positive probability. Moreover, AVSTM guarantees lock freedom. Owing to its permissiveness, AVSTM outperforms other STMs by up to 40% in read dominated workloads in high contention scenarios. But, in low contention scenarios, the book-keeping done by AVSTM to achieve permissiveness makes AVSTM, on average, 20-30% worse than existing STMs."}],"main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/permissiveness_in_transactional_memories.pdf"}],"doi":"10.1007/978-3-540-87779-0_21","publication_status":"published"},{"year":"2008","publist_id":"1071","conference":{"name":"CONCUR: Concurrency Theory"},"page":"21 - 35","title":"Completeness and nondeterminism in model checking transactional memories","author":[{"full_name":"Guerraoui, Rachid","first_name":"Rachid","last_name":"Guerraoui"},{"orcid":"0000−0002−2985−7724","last_name":"Henzinger","first_name":"Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","full_name":"Thomas Henzinger"},{"last_name":"Singh","id":"4DAE2708-F248-11E8-B48F-1D18A9856A87","first_name":"Vasu","full_name":"Vasu Singh"}],"date_updated":"2021-01-12T07:56:35Z","publisher":"Schloss Dagstuhl - Leibniz-Zentrum für Informatik","acknowledgement":"This research was supported by the Swiss National Science Foundation.","month":"07","intvolume":"      5201","date_published":"2008-07-30T00:00:00Z","alternative_title":["LNCS"],"publication_status":"published","doi":"10.1007/978-3-540-85361-9_6","main_file_link":[{"url":"http://pub.ist.ac.at/%7Etah/Publications/completeness_and_nondeterminism_in_model_checking_transactional_memories.pdf","open_access":"0"}],"status":"public","quality_controlled":0,"day":"30","date_created":"2018-12-11T12:08:35Z","_id":"4387","type":"conference","abstract":[{"lang":"eng","text":"Software transactional memory (STM) offers a disciplined concurrent programming model for exploiting the parallelism of modern processor architectures. This paper presents the first deterministic specification automata for strict serializability and opacity in STMs. Using an antichain-based tool, we show our deterministic specifications to be equivalent to more intuitive, nondeterministic specification automata (which are too large to be determinized automatically). Using deterministic specification automata, we obtain a complete verification tool for STMs. We also show how to model and verify contention management within STMs. We automatically check the opacity of popular STM algorithms, such as TL2 and DSTM, with a universal contention manager. The universal contention manager is nondeterministic and establishes correctness for all possible contention management schemes."}],"citation":{"apa":"Guerraoui, R., Henzinger, T. A., &#38; Singh, V. (2008). Completeness and nondeterminism in model checking transactional memories (Vol. 5201, pp. 21–35). Presented at the CONCUR: Concurrency Theory, Schloss Dagstuhl - Leibniz-Zentrum für Informatik. <a href=\"https://doi.org/10.1007/978-3-540-85361-9_6\">https://doi.org/10.1007/978-3-540-85361-9_6</a>","mla":"Guerraoui, Rachid, et al. <i>Completeness and Nondeterminism in Model Checking Transactional Memories</i>. Vol. 5201, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2008, pp. 21–35, doi:<a href=\"https://doi.org/10.1007/978-3-540-85361-9_6\">10.1007/978-3-540-85361-9_6</a>.","ama":"Guerraoui R, Henzinger TA, Singh V. Completeness and nondeterminism in model checking transactional memories. In: Vol 5201. Schloss Dagstuhl - Leibniz-Zentrum für Informatik; 2008:21-35. doi:<a href=\"https://doi.org/10.1007/978-3-540-85361-9_6\">10.1007/978-3-540-85361-9_6</a>","ieee":"R. Guerraoui, T. A. Henzinger, and V. Singh, “Completeness and nondeterminism in model checking transactional memories,” presented at the CONCUR: Concurrency Theory, 2008, vol. 5201, pp. 21–35.","ista":"Guerraoui R, Henzinger TA, Singh V. 2008. Completeness and nondeterminism in model checking transactional memories. CONCUR: Concurrency Theory, LNCS, vol. 5201, 21–35.","short":"R. Guerraoui, T.A. Henzinger, V. Singh, in:, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2008, pp. 21–35.","chicago":"Guerraoui, Rachid, Thomas A Henzinger, and Vasu Singh. “Completeness and Nondeterminism in Model Checking Transactional Memories,” 5201:21–35. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2008. <a href=\"https://doi.org/10.1007/978-3-540-85361-9_6\">https://doi.org/10.1007/978-3-540-85361-9_6</a>."},"extern":1,"volume":5201},{"quality_controlled":0,"day":"01","status":"public","date_created":"2018-12-11T12:08:38Z","_id":"4397","type":"conference","citation":{"apa":"Beyer, D., Zufferey, D., &#38; Majumdar, R. (2008). CSIsat: Interpolation for LA+EUF (pp. 304–308). Presented at the CAV: Computer Aided Verification, Springer.","mla":"Beyer, Dirk, et al. <i>CSIsat: Interpolation for LA+EUF</i>. Springer, 2008, pp. 304–08.","ista":"Beyer D, Zufferey D, Majumdar R. 2008. CSIsat: Interpolation for LA+EUF. CAV: Computer Aided Verification, LNCS 5123, , 304–308.","short":"D. Beyer, D. Zufferey, R. Majumdar, in:, Springer, 2008, pp. 304–308.","ieee":"D. Beyer, D. Zufferey, and R. Majumdar, “CSIsat: Interpolation for LA+EUF,” presented at the CAV: Computer Aided Verification, 2008, pp. 304–308.","ama":"Beyer D, Zufferey D, Majumdar R. CSIsat: Interpolation for LA+EUF. In: Springer; 2008:304-308.","chicago":"Beyer, Dirk, Damien Zufferey, and Ritankar Majumdar. “CSIsat: Interpolation for LA+EUF,” 304–8. Springer, 2008."},"extern":1,"publication_status":"published","title":"CSIsat: Interpolation for LA+EUF","author":[{"full_name":"Beyer, Dirk","last_name":"Beyer","first_name":"Dirk"},{"id":"4397AC76-F248-11E8-B48F-1D18A9856A87","first_name":"Damien","orcid":"0000-0002-3197-8736","last_name":"Zufferey","full_name":"Damien Zufferey"},{"first_name":"Ritankar","last_name":"Majumdar","full_name":"Majumdar, Ritankar S"}],"date_updated":"2021-01-12T07:56:40Z","publisher":"Springer","month":"01","alternative_title":["LNCS 5123"],"date_published":"2008-01-01T00:00:00Z","year":"2008","publist_id":"1060","conference":{"name":"CAV: Computer Aided Verification"},"page":"304 - 308"},{"doi":"1545","publication_status":"published","main_file_link":[{"open_access":"0","url":"http://www.usenix.org/event/evt08/tech/full_papers/aviv/aviv.pdf"}],"day":"29","status":"public","quality_controlled":0,"_id":"4400","date_created":"2018-12-11T12:08:39Z","type":"conference","extern":1,"citation":{"apa":"Aviv, A., Cerny, P., Clark, S., Cronin, E., Shah, G., Sherr, M., &#38; Blaze, M. (2008). Security Evaluation of ES&#38;amp;S Voting Machines and Election Management System. Presented at the Usenix/ Accurate Electronic Voting Technology Workshop (EVT) 08, USENIX. <a href=\"https://doi.org/1545\">https://doi.org/1545</a>","mla":"Aviv, Adam, et al. <i>Security Evaluation of ES&#38;amp;S Voting Machines and Election Management System</i>. USENIX, 2008, doi:<a href=\"https://doi.org/1545\">1545</a>.","short":"A. Aviv, P. Cerny, S. Clark, E. Cronin, G. Shah, M. Sherr, M. Blaze, in:, USENIX, 2008.","ista":"Aviv A, Cerny P, Clark S, Cronin E, Shah G, Sherr M, Blaze M. 2008. Security Evaluation of ES&#38;amp;S Voting Machines and Election Management System. Usenix/ Accurate Electronic Voting Technology Workshop (EVT) 08.","ieee":"A. Aviv <i>et al.</i>, “Security Evaluation of ES&#38;amp;S Voting Machines and Election Management System,” presented at the Usenix/ Accurate Electronic Voting Technology Workshop (EVT) 08, 2008.","ama":"Aviv A, Cerny P, Clark S, et al. Security Evaluation of ES&#38;amp;S Voting Machines and Election Management System. In: USENIX; 2008. doi:<a href=\"https://doi.org/1545\">1545</a>","chicago":"Aviv, Adam, Pavol Cerny, Sandy Clark, Eric Cronin, Gaurav Shah, Micah Sherr, and Matt Blaze. “Security Evaluation of ES&#38;amp;S Voting Machines and Election Management System.” USENIX, 2008. <a href=\"https://doi.org/1545\">https://doi.org/1545</a>."},"year":"2008","publist_id":"1057","conference":{"name":"Usenix/ Accurate Electronic Voting Technology Workshop (EVT) 08"},"title":"Security Evaluation of ES&amp;S Voting Machines and Election Management System","author":[{"last_name":"Aviv","first_name":"Adam","full_name":"Aviv,Adam J."},{"last_name":"Cerny","id":"4DCBEFFE-F248-11E8-B48F-1D18A9856A87","first_name":"Pavol","full_name":"Pavol Cerny"},{"full_name":"Clark,Sandy","first_name":"Sandy","last_name":"Clark"},{"full_name":"Cronin,Eric","last_name":"Cronin","first_name":"Eric"},{"last_name":"Shah","first_name":"Gaurav","full_name":"Shah,Gaurav"},{"full_name":"Sherr,Micah","first_name":"Micah","last_name":"Sherr"},{"full_name":"Blaze,Matt","first_name":"Matt","last_name":"Blaze"}],"date_updated":"2021-01-12T07:56:42Z","publisher":"USENIX","month":"07","date_published":"2008-07-29T00:00:00Z"},{"publisher":"University of California, Berkeley","month":"09","date_published":"2008-09-01T00:00:00Z","oa":1,"author":[{"last_name":"Prabhu","first_name":"Vinayak","full_name":"Prabhu, Vinayak"}],"user_id":"8b945eb4-e2f2-11eb-945a-df72226e66a9","title":"Games for the verification of timed systems","date_updated":"2022-02-14T14:35:11Z","publist_id":"319","page":"1 - 137","article_processing_charge":"No","year":"2008","language":[{"iso":"eng"}],"type":"dissertation","abstract":[{"text":"Models of timed systems must incorporate not only the sequence of system events, but the timings of these events as well to capture the real-time aspects of physical systems. Timed automata are models of real-time systems in which states consist of discrete locations and values for real-time clocks. The presence of real-time clocks leads to an uncountable state space. This thesis studies verification problems on timed automata in a game theoretic framework.\r\n\r\nFor untimed systems, two systems are close if every sequence of events of one system is also observable in the second system. For timed systems, the difference in timings of the two corresponding sequences is also of importance. We propose the notion of bisimulation distance which quantifies timing differences; if the bisimulation distance between two systems is epsilon, then (a) every sequence of events of one system has a corresponding matching sequence in the other, and (b) the timings of matching events in between the two corresponding traces do not differ by more than epsilon. We show that we can compute the bisimulation distance between two timed automata to within any desired degree of accuracy. We also show that the timed verification logic TCTL is robust with respect to our notion of quantitative bisimilarity, in particular, if a system satisfies a formula, then every close system satisfies a close formula.\r\n\r\nTimed games are used for distinguishing between the actions of several agents, typically a controller and an environment. The controller must achieve its objective against all possible choices of the environment. The modeling of the passage of time leads to the presence of zeno executions, and corresponding unrealizable strategies of the controller which may achieve objectives by blocking time. We disallow such unreasonable strategies by restricting all agents to use only receptive strategies --strategies which while not being required to ensure time divergence by any agent, are such that no agent is responsible for blocking time. Time divergence is guaranteed when all players use receptive strategies. We show that timed automaton games with receptive strategies can be solved by a reduction to finite state turn based game graphs. We define the logic timed alternating-time temporal logic for verification of timed automaton games and show that the logic can be model checked in EXPTIME. We also show that the minimum time required by an agent to reach a desired location, and the maximum time an agent can stay safe within a set of locations, against all possible actions of its adversaries are both computable.\r\n\r\nWe next study the memory requirements of winning strategies for timed automaton games. We prove that finite memory strategies suffice for safety objectives, and that winning strategies for reachability objectives may require infinite memory in general. We introduce randomized strategies in which an agent can propose a probabilistic distribution of moves and show that finite memory randomized strategies suffice for all omega-regular objectives. We also show that while randomization helps in simplifying winning strategies, and thus allows the construction of simpler controllers, it does not help a player in winning at more states, and thus does not allow the construction of more powerful controllers.\r\n\r\nFinally we study robust winning strategies in timed games. In a physical system, a controller may propose an action together with a time delay, but the action cannot be assumed to be executed at the exact proposed time delay. We present robust strategies which incorporate such jitters and show that the set of states from which an agent can win robustly is computable.","lang":"eng"}],"citation":{"ieee":"V. Prabhu, “Games for the verification of timed systems,” University of California, Berkeley, 2008.","short":"V. Prabhu, Games for the Verification of Timed Systems, University of California, Berkeley, 2008.","ista":"Prabhu V. 2008. Games for the verification of timed systems. University of California, Berkeley.","ama":"Prabhu V. Games for the verification of timed systems. 2008:1-137.","chicago":"Prabhu, Vinayak. “Games for the Verification of Timed Systems.” University of California, Berkeley, 2008.","apa":"Prabhu, V. (2008). <i>Games for the verification of timed systems</i>. University of California, Berkeley.","mla":"Prabhu, Vinayak. <i>Games for the Verification of Timed Systems</i>. University of California, Berkeley, 2008, pp. 1–137."},"extern":"1","supervisor":[{"orcid":"0000-0002-2985-7724","last_name":"Henzinger","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","full_name":"Henzinger, Thomas A"},{"first_name":"John","last_name":"Steel","full_name":"Steel, John"},{"last_name":"Varaiya","first_name":"Pravin","full_name":"Varaiya, Pravin"}],"status":"public","day":"01","date_created":"2018-12-11T12:08:42Z","_id":"4409","publication_status":"published","main_file_link":[{"url":"https://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-97.html","open_access":"1"}],"degree_awarded":"PhD","oa_version":"None"},{"publisher":"University of California, Berkeley","acknowledgement":"978-0-549-83480-9","date_published":"2008-01-01T00:00:00Z","month":"01","user_id":"8b945eb4-e2f2-11eb-945a-df72226e66a9","title":"Compositionality in deterministic real-time embedded systems","author":[{"last_name":"Matic","first_name":"Slobodan","full_name":"Matic, Slobodan"}],"date_updated":"2022-02-14T14:08:50Z","publist_id":"316","page":"1 - 148","article_processing_charge":"No","year":"2008","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Many computing applications, especially those in safety critical embedded systems, require highly predictable timing properties. However, time is often not present in the prevailing computing and networking abstractions. In fact, most advances in computer architecture, software, and networking favor average-case performance over timing predictability. This thesis studies several methods for the design of concurrent and/or distributed embedded systems with precise timing guarantees. The focus is on flexible and compositional methods for programming and verification of the timing properties. The presented methods together with related formalisms cover two levels of design: (1) Programming language/model level. We propose the distributed variant of Giotto, a coordination programming language with an explicit temporal semantics—the logical execution time (LET) semantics. The LET of a task is an interval of time that specifies the time instants at which task inputs and outputs become available (task release and termination instants). The LET of a task is always non-zero. This allows us to communicate values across the network without changing the timing information of the task, and without introducing nondeterminism. We show how this methodology supports distributed code generation for distributed real-time systems. The method gives up some performance in favor of composability and predictability. We characterize the tradeoff by comparing the LET semantics with the semantics used in Simulink. (2) Abstract task graph level. We study interface-based design and verification of applications represented with task graphs. We consider task sequence graphs with general event models, and cyclic graphs with periodic event models with jitter and phase. Here an interface of a component exposes time and resource constraints of the component. Together with interfaces we formally define interface composition operations and the refinement relation. For efficient and flexible composability checking two properties are important: incremental design and independent refinement. According to the incremental design property the composition of interfaces can be performed in any order, even if interfaces for some components are not known. The refinement relation is defined such that in a design we can always substitute a refined interface for an abstract one. We show that the framework supports independent refinement, i.e., the refinement relation is preserved under composition operations."}],"type":"dissertation","citation":{"short":"S. Matic, Compositionality in Deterministic Real-Time Embedded Systems, University of California, Berkeley, 2008.","ieee":"S. Matic, “Compositionality in deterministic real-time embedded systems,” University of California, Berkeley, 2008.","ista":"Matic S. 2008. Compositionality in deterministic real-time embedded systems. University of California, Berkeley.","ama":"Matic S. Compositionality in deterministic real-time embedded systems. 2008:1-148.","chicago":"Matic, Slobodan. “Compositionality in Deterministic Real-Time Embedded Systems.” University of California, Berkeley, 2008.","apa":"Matic, S. (2008). <i>Compositionality in deterministic real-time embedded systems</i>. University of California, Berkeley.","mla":"Matic, Slobodan. <i>Compositionality in Deterministic Real-Time Embedded Systems</i>. University of California, Berkeley, 2008, pp. 1–148."},"extern":"1","status":"public","day":"01","supervisor":[{"orcid":"0000-0002-2985-7724","last_name":"Henzinger","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","full_name":"Henzinger, Thomas A"},{"last_name":"Lee","first_name":"Edward","full_name":"Lee, Edward"},{"full_name":"Sengupta, Raja","first_name":"Raja","last_name":"Sengupta"}],"_id":"4415","date_created":"2018-12-11T12:08:44Z","publication_status":"published","degree_awarded":"PhD","oa_version":"None"},{"date_updated":"2021-01-12T07:57:04Z","author":[{"full_name":"Thomas Henzinger","last_name":"Henzinger","orcid":"0000−0002−2985−7724","first_name":"Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87"},{"last_name":"Hottelier","first_name":"Thibaud","full_name":"Hottelier, Thibaud"},{"full_name":"Kovács, Laura","last_name":"Kovács","first_name":"Laura"}],"title":"Valigator: A verification tool with bound and invariant generation","date_published":"2008-11-13T00:00:00Z","alternative_title":["LNCS"],"intvolume":"      5330","month":"11","publisher":"Springer","acknowledgement":"This research was supported by the Swiss NSF.","year":"2008","page":"333 - 342","conference":{"name":"LPAR: Logic for Programming, Artificial Intelligence, and Reasoning"},"publist_id":"277","_id":"4452","date_created":"2018-12-11T12:08:55Z","status":"public","day":"13","quality_controlled":0,"volume":5330,"extern":1,"citation":{"mla":"Henzinger, Thomas A., et al. <i>Valigator: A Verification Tool with Bound and Invariant Generation</i>. Vol. 5330, Springer, 2008, pp. 333–42, doi:<a href=\"https://doi.org/10.1007/978-3-540-89439-1_24\">10.1007/978-3-540-89439-1_24</a>.","apa":"Henzinger, T. A., Hottelier, T., &#38; Kovács, L. (2008). Valigator: A verification tool with bound and invariant generation (Vol. 5330, pp. 333–342). Presented at the LPAR: Logic for Programming, Artificial Intelligence, and Reasoning, Springer. <a href=\"https://doi.org/10.1007/978-3-540-89439-1_24\">https://doi.org/10.1007/978-3-540-89439-1_24</a>","chicago":"Henzinger, Thomas A, Thibaud Hottelier, and Laura Kovács. “Valigator: A Verification Tool with Bound and Invariant Generation,” 5330:333–42. Springer, 2008. <a href=\"https://doi.org/10.1007/978-3-540-89439-1_24\">https://doi.org/10.1007/978-3-540-89439-1_24</a>.","ama":"Henzinger TA, Hottelier T, Kovács L. Valigator: A verification tool with bound and invariant generation. In: Vol 5330. Springer; 2008:333-342. doi:<a href=\"https://doi.org/10.1007/978-3-540-89439-1_24\">10.1007/978-3-540-89439-1_24</a>","ieee":"T. A. Henzinger, T. Hottelier, and L. Kovács, “Valigator: A verification tool with bound and invariant generation,” presented at the LPAR: Logic for Programming, Artificial Intelligence, and Reasoning, 2008, vol. 5330, pp. 333–342.","short":"T.A. Henzinger, T. Hottelier, L. Kovács, in:, Springer, 2008, pp. 333–342.","ista":"Henzinger TA, Hottelier T, Kovács L. 2008. Valigator: A verification tool with bound and invariant generation. LPAR: Logic for Programming, Artificial Intelligence, and Reasoning, LNCS, vol. 5330, 333–342."},"abstract":[{"text":"We describe Valigator, a software tool for imperative program verification that efficiently combines symbolic computation and automated reasoning in a uniform framework. The system offers support for automatically generating and proving verification conditions and, most importantly, for automatically inferring loop invariants and bound assertions by means of symbolic summation, Gröbner basis computation, and quantifier elimination. We present general principles of the implementation and illustrate them on examples.","lang":"eng"}],"type":"conference","publication_status":"published","main_file_link":[{"url":"http://pub.ist.ac.at/%7Etah/Publications/valigator.pdf","open_access":"0"}],"doi":"10.1007/978-3-540-89439-1_24"},{"main_file_link":[{"url":"http://pub.ist.ac.at/%7Etah/Publications/two_challenges_in_embedded_systems_design.pdf","open_access":"0"}],"publication_status":"published","doi":"10.1098/rsta.2008.0141","publication":"Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences","quality_controlled":0,"day":"31","status":"public","_id":"4509","date_created":"2018-12-11T12:09:13Z","type":"journal_article","abstract":[{"text":"I discuss two main challenges in embedded systems design: the challenge to build predictable systems, and that to build robust systems. I suggest how predictability can be formalized as a form of determinism, and robustness as a form of continuity.","lang":"eng"}],"citation":{"apa":"Henzinger, T. A. (2008). Two challenges in embedded systems design: Predictability and robustness. <i>Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences</i>. Royal Society of London. <a href=\"https://doi.org/10.1098/rsta.2008.0141\">https://doi.org/10.1098/rsta.2008.0141</a>","mla":"Henzinger, Thomas A. “Two Challenges in Embedded Systems Design: Predictability and Robustness.” <i>Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences</i>, vol. 366, no. 1881, Royal Society of London, 2008, pp. 3727–36, doi:<a href=\"https://doi.org/10.1098/rsta.2008.0141\">10.1098/rsta.2008.0141</a>.","ama":"Henzinger TA. Two challenges in embedded systems design: Predictability and robustness. <i>Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences</i>. 2008;366(1881):3727-3736. doi:<a href=\"https://doi.org/10.1098/rsta.2008.0141\">10.1098/rsta.2008.0141</a>","short":"T.A. Henzinger, Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences 366 (2008) 3727–3736.","ista":"Henzinger TA. 2008. Two challenges in embedded systems design: Predictability and robustness. Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences. 366(1881), 3727–3736.","ieee":"T. A. Henzinger, “Two challenges in embedded systems design: Predictability and robustness,” <i>Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences</i>, vol. 366, no. 1881. Royal Society of London, pp. 3727–3736, 2008.","chicago":"Henzinger, Thomas A. “Two Challenges in Embedded Systems Design: Predictability and Robustness.” <i>Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences</i>. Royal Society of London, 2008. <a href=\"https://doi.org/10.1098/rsta.2008.0141\">https://doi.org/10.1098/rsta.2008.0141</a>."},"extern":1,"volume":366,"year":"2008","publist_id":"219","page":"3727 - 3736","issue":"1881","author":[{"full_name":"Thomas Henzinger","orcid":"0000−0002−2985−7724","last_name":"Henzinger","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A"}],"title":"Two challenges in embedded systems design: Predictability and robustness","date_updated":"2021-01-12T07:59:19Z","publisher":"Royal Society of London","intvolume":"       366","month":"07","date_published":"2008-07-31T00:00:00Z"},{"page":"147 - 158","conference":{"name":"POPL: Principles of Programming Languages"},"publist_id":"208","year":"2008","month":"01","date_published":"2008-01-01T00:00:00Z","publisher":"ACM","date_updated":"2021-01-12T07:59:25Z","title":"Proving non-termination","author":[{"id":"335E5684-F248-11E8-B48F-1D18A9856A87","first_name":"Ashutosh","last_name":"Gupta","full_name":"Ashutosh Gupta"},{"full_name":"Thomas Henzinger","orcid":"0000−0002−2985−7724","last_name":"Henzinger","first_name":"Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87"},{"first_name":"Ritankar","last_name":"Majumdar","full_name":"Majumdar, Ritankar S"},{"full_name":"Rybalchenko, Andrey","last_name":"Rybalchenko","first_name":"Andrey"},{"last_name":"Xu","first_name":"Ru","full_name":"Xu, Ru-Gang"}],"main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/proving_non-termination.pdf"}],"publication_status":"published","doi":"10.1145/1328438.1328459","citation":{"apa":"Gupta, A., Henzinger, T. A., Majumdar, R., Rybalchenko, A., &#38; Xu, R. (2008). Proving non-termination (pp. 147–158). Presented at the POPL: Principles of Programming Languages, ACM. <a href=\"https://doi.org/10.1145/1328438.1328459\">https://doi.org/10.1145/1328438.1328459</a>","mla":"Gupta, Ashutosh, et al. <i>Proving Non-Termination</i>. ACM, 2008, pp. 147–58, doi:<a href=\"https://doi.org/10.1145/1328438.1328459\">10.1145/1328438.1328459</a>.","ieee":"A. Gupta, T. A. Henzinger, R. Majumdar, A. Rybalchenko, and R. Xu, “Proving non-termination,” presented at the POPL: Principles of Programming Languages, 2008, pp. 147–158.","short":"A. Gupta, T.A. Henzinger, R. Majumdar, A. Rybalchenko, R. Xu, in:, ACM, 2008, pp. 147–158.","ista":"Gupta A, Henzinger TA, Majumdar R, Rybalchenko A, Xu R. 2008. Proving non-termination. POPL: Principles of Programming Languages, 147–158.","ama":"Gupta A, Henzinger TA, Majumdar R, Rybalchenko A, Xu R. Proving non-termination. In: ACM; 2008:147-158. doi:<a href=\"https://doi.org/10.1145/1328438.1328459\">10.1145/1328438.1328459</a>","chicago":"Gupta, Ashutosh, Thomas A Henzinger, Ritankar Majumdar, Andrey Rybalchenko, and Ru Xu. “Proving Non-Termination,” 147–58. ACM, 2008. <a href=\"https://doi.org/10.1145/1328438.1328459\">https://doi.org/10.1145/1328438.1328459</a>."},"extern":1,"type":"conference","abstract":[{"lang":"eng","text":"The search for proof and the search for counterexamples (bugs) are complementary activities that need to be pursued concurrently in order to maximize the practical success rate of verification tools.While this is well-understood in safety verification, the current focus of liveness verification has been almost exclusively on the search for termination proofs. A counterexample to termination is an infinite programexecution. In this paper, we propose a method to search for such counterexamples. The search proceeds in two phases. We first dynamically enumerate lasso-shaped candidate paths for counterexamples, and then statically prove their feasibility. We illustrate the utility of our nontermination prover, called TNT, on several nontrivial examples, some of which require bit-level reasoning about integer representations."}],"date_created":"2018-12-11T12:09:17Z","_id":"4521","day":"01","status":"public","quality_controlled":0},{"publication_status":"published","oa_version":"None","abstract":[{"text":"Complex requirements, time-to-market pressure and regulatory constraints have made the designing of embedded systems extremely challenging. This is evident by the increase in effort and expenditure for design of safety-driven real-time control-dominated applications like automotive and avionic controllers. Design processes are often challenged by lack of proper programming tools for specifying and verifying critical requirements (e.g. timing and reliability) of such applications. Platform based design, an approach for designing embedded systems, addresses the above concerns by separating requirement from architecture. The requirement specifies the intended behavior of an application while the architecture specifies the guarantees (e.g. execution speed, failure rate etc). An implementation, a mapping of the requirement on the architecture, is then analyzed for correctness. The orthogonalization of concerns makes the specification and analyses simpler. An effective use of such design methodology has been proposed in Logical Execution Time (LET) model of real-time tasks. The model separates the timing requirements (specified by release and termination instances of a task) from the architecture guarantees (specified by worst-case execution time of the task).\r\n\r\nThis dissertation proposes a coordination language, Hierarchical Timing Language (HTL), that captures the timing and reliability requirements of real-time applications. An implementation of the program on an architecture is then analyzed to check whether desired timing and reliability requirements are met or not. The core framework extends the LET model by accounting for reliability and refinement. The reliability model separates the reliability requirements of tasks from the reliability guarantees of the architecture. The requirement expresses the desired long-term reliability while the architecture provides a short-term reliability guarantee (e.g. failure rate for each iteration). The analysis checks if the short-term guarantee ensures the desired long-term reliability. The refinement model allows replacing a task by another task during program execution. Refinement preserves schedulability and reliability, i.e., if a refined task is schedulable and reliable for an implementation, then the refining task is also schedulable and reliable for the implementation. Refinement helps in concise specification without overloading analysis.\r\n\r\nThe work presents the formal model, the analyses (both with and without refinement), and a compiler for HTL programs. The compiler checks composition and refinement constraints, performs schedulability and reliability analyses, and generates code for implementation of an HTL program on a virtual machine. Three real-time controllers, one each from automatic control, automotive control and avionic control, are used to illustrate the steps in modeling and analyzing HTL programs.","lang":"eng"}],"type":"dissertation","extern":"1","citation":{"ista":"Ghosal A. 2008. A hierarchical coordination language for reliable real-time tasks. University of California, Berkeley.","short":"A. Ghosal, A Hierarchical Coordination Language for Reliable Real-Time Tasks, University of California, Berkeley, 2008.","ieee":"A. Ghosal, “A hierarchical coordination language for reliable real-time tasks,” University of California, Berkeley, 2008.","ama":"Ghosal A. A hierarchical coordination language for reliable real-time tasks. 2008:1-210.","chicago":"Ghosal, Arkadeb. “A Hierarchical Coordination Language for Reliable Real-Time Tasks.” University of California, Berkeley, 2008.","apa":"Ghosal, A. (2008). <i>A hierarchical coordination language for reliable real-time tasks</i>. University of California, Berkeley.","mla":"Ghosal, Arkadeb. <i>A Hierarchical Coordination Language for Reliable Real-Time Tasks</i>. University of California, Berkeley, 2008, pp. 1–210."},"day":"31","status":"public","supervisor":[{"full_name":"Sangiovanni-Vincentelli, Alberto","last_name":"Sangiovanni-Vincentelli","first_name":"Alberto"},{"full_name":"Henzinger, Thomas A","first_name":"Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","orcid":"0000-0002-2985-7724","last_name":"Henzinger"},{"first_name":"Edward","last_name":"Lee","full_name":"Lee, Edward"},{"full_name":"Hedrick, Karl","last_name":"Hedrick","first_name":"Karl"}],"date_created":"2018-12-11T12:09:18Z","_id":"4524","publist_id":"199","article_processing_charge":"No","page":"1 - 210","year":"2008","language":[{"iso":"eng"}],"publisher":"University of California, Berkeley","acknowledgement":"978-0-549-83679-7","date_published":"2008-01-31T00:00:00Z","month":"01","author":[{"last_name":"Ghosal","first_name":"Arkadeb","full_name":"Ghosal, Arkadeb"}],"title":"A hierarchical coordination language for reliable real-time tasks","user_id":"2DF688A6-F248-11E8-B48F-1D18A9856A87","date_updated":"2021-01-12T07:59:26Z"},{"year":"2008","publist_id":"196","conference":{"name":"FMSB: Formal Methods in Systems Biology"},"page":"17 - 32","author":[{"first_name":"Jasmin","last_name":"Fisher","full_name":"Fisher, Jasmin"},{"id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","last_name":"Henzinger","orcid":"0000−0002−2985−7724","full_name":"Thomas Henzinger"},{"full_name":"Maria Mateescu","last_name":"Mateescu","first_name":"Maria","id":"3B43276C-F248-11E8-B48F-1D18A9856A87"},{"full_name":"Piterman, Nir","first_name":"Nir","last_name":"Piterman"}],"title":"Bounded asynchrony: Concurrency for modeling cell-cell interactions","date_updated":"2021-01-12T07:59:27Z","acknowledgement":"Supported in part by the Swiss National Science Foundation (grant 205321-111840).","publisher":"Springer","alternative_title":["LNCS"],"date_published":"2008-05-26T00:00:00Z","month":"05","intvolume":"      5054","main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/bounded_asynchrony.pdf"}],"doi":"10.1007/978-3-540-68413-8_2","publication_status":"published","quality_controlled":0,"status":"public","day":"26","_id":"4527","date_created":"2018-12-11T12:09:19Z","abstract":[{"lang":"eng","text":"We introduce bounded asynchrony, a notion of concurrency tailored to the modeling of biological cell-cell interactions. Bounded asynchrony is the result of a scheduler that bounds the number of steps that one process gets ahead of other processes; this allows the components of a system to move independently while keeping them coupled. Bounded asynchrony accurately reproduces the experimental observations made about certain cell-cell interactions: its constrained nondeterminism captures the variability observed in cells that, although equally potent, assume distinct fates. Real-life cells are not “scheduled”, but we show that distributed real-time behavior can lead to component interactions that are observationally equivalent to bounded asynchrony; this provides a possible mechanistic explanation for the phenomena observed during cell fate specification.\nWe use model checking to determine cell fates. The nondeterminism of bounded asynchrony causes state explosion during model checking, but partial-order methods are not directly applicable. We present a new algorithm that reduces the number of states that need to be explored: our optimization takes advantage of the bounded-asynchronous progress and the spatially local interactions of components that model cells. We compare our own communication-based reduction with partial-order reduction (on a restricted form of bounded asynchrony) and experiments illustrate that our algorithm leads to significant savings."}],"type":"conference","volume":5054,"extern":1,"citation":{"apa":"Fisher, J., Henzinger, T. A., Mateescu, M., &#38; Piterman, N. (2008). Bounded asynchrony: Concurrency for modeling cell-cell interactions (Vol. 5054, pp. 17–32). Presented at the FMSB: Formal Methods in Systems Biology, Springer. <a href=\"https://doi.org/10.1007/978-3-540-68413-8_2\">https://doi.org/10.1007/978-3-540-68413-8_2</a>","mla":"Fisher, Jasmin, et al. <i>Bounded Asynchrony: Concurrency for Modeling Cell-Cell Interactions</i>. Vol. 5054, Springer, 2008, pp. 17–32, doi:<a href=\"https://doi.org/10.1007/978-3-540-68413-8_2\">10.1007/978-3-540-68413-8_2</a>.","ama":"Fisher J, Henzinger TA, Mateescu M, Piterman N. Bounded asynchrony: Concurrency for modeling cell-cell interactions. In: Vol 5054. Springer; 2008:17-32. doi:<a href=\"https://doi.org/10.1007/978-3-540-68413-8_2\">10.1007/978-3-540-68413-8_2</a>","short":"J. Fisher, T.A. Henzinger, M. Mateescu, N. Piterman, in:, Springer, 2008, pp. 17–32.","ista":"Fisher J, Henzinger TA, Mateescu M, Piterman N. 2008. Bounded asynchrony: Concurrency for modeling cell-cell interactions. FMSB: Formal Methods in Systems Biology, LNCS, vol. 5054, 17–32.","ieee":"J. Fisher, T. A. Henzinger, M. Mateescu, and N. Piterman, “Bounded asynchrony: Concurrency for modeling cell-cell interactions,” presented at the FMSB: Formal Methods in Systems Biology, 2008, vol. 5054, pp. 17–32.","chicago":"Fisher, Jasmin, Thomas A Henzinger, Maria Mateescu, and Nir Piterman. “Bounded Asynchrony: Concurrency for Modeling Cell-Cell Interactions,” 5054:17–32. Springer, 2008. <a href=\"https://doi.org/10.1007/978-3-540-68413-8_2\">https://doi.org/10.1007/978-3-540-68413-8_2</a>."}},{"quality_controlled":0,"status":"public","day":"01","date_created":"2018-12-11T12:09:20Z","_id":"4532","abstract":[{"lang":"eng","text":"We consider the equivalence problem for labeled Markov chains (LMCs), where each state is labeled with an observation. Two LMCs are equivalent if every finite sequence of observations has the same probability of occurrence in the two LMCs. We show that equivalence can be decided in polynomial time, using a reduction to the equivalence problem for probabilistic automata, which is known to be solvable in polynomial time. We provide an alternative algorithm to solve the equivalence problem, which is based on a new definition of bisimulation for probabilistic automata. We also extend the technique to decide the equivalence of weighted probabilistic automata."}],"type":"journal_article","volume":19,"citation":{"mla":"Doyen, Laurent, et al. “Equivalence of Labeled Markov Chains.” <i>International Journal of Foundations of Computer Science</i>, vol. 19, no. 3, World Scientific Publishing, 2008, pp. 549–63, doi:<a href=\"https://doi.org/10.1142/S0129054108005814 \">10.1142/S0129054108005814 </a>.","apa":"Doyen, L., Henzinger, T. A., &#38; Raskin, J. (2008). Equivalence of labeled Markov chains. <i>International Journal of Foundations of Computer Science</i>. World Scientific Publishing. <a href=\"https://doi.org/10.1142/S0129054108005814 \">https://doi.org/10.1142/S0129054108005814 </a>","chicago":"Doyen, Laurent, Thomas A Henzinger, and Jean Raskin. “Equivalence of Labeled Markov Chains.” <i>International Journal of Foundations of Computer Science</i>. World Scientific Publishing, 2008. <a href=\"https://doi.org/10.1142/S0129054108005814 \">https://doi.org/10.1142/S0129054108005814 </a>.","ama":"Doyen L, Henzinger TA, Raskin J. Equivalence of labeled Markov chains. <i>International Journal of Foundations of Computer Science</i>. 2008;19(3):549-563. doi:<a href=\"https://doi.org/10.1142/S0129054108005814 \">10.1142/S0129054108005814 </a>","ieee":"L. Doyen, T. A. Henzinger, and J. Raskin, “Equivalence of labeled Markov chains,” <i>International Journal of Foundations of Computer Science</i>, vol. 19, no. 3. World Scientific Publishing, pp. 549–563, 2008.","short":"L. Doyen, T.A. Henzinger, J. Raskin, International Journal of Foundations of Computer Science 19 (2008) 549–563.","ista":"Doyen L, Henzinger TA, Raskin J. 2008. Equivalence of labeled Markov chains. International Journal of Foundations of Computer Science. 19(3), 549–563."},"extern":1,"publication":"International Journal of Foundations of Computer Science","publication_status":"published","main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/equivalence_of_labeled_markov_chains.pdf"}],"doi":"10.1142/S0129054108005814 ","author":[{"last_name":"Doyen","first_name":"Laurent","full_name":"Doyen, Laurent"},{"full_name":"Thomas Henzinger","orcid":"0000−0002−2985−7724","last_name":"Henzinger","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A"},{"full_name":"Raskin, Jean-François","first_name":"Jean","last_name":"Raskin"}],"title":"Equivalence of labeled Markov chains","issue":"3","date_updated":"2021-01-12T07:59:30Z","publisher":"World Scientific Publishing","date_published":"2008-06-01T00:00:00Z","month":"06","intvolume":"        19","year":"2008","publist_id":"192","page":"549 - 563"},{"publication_status":"published","main_file_link":[{"url":"http://pub.ist.ac.at/%7Etah/Publications/interface_theories_with_component_reuse.pdf","open_access":"0"}],"doi":"10.1145/1450058.1450070","date_created":"2018-12-11T12:09:21Z","_id":"4533","status":"public","day":"01","quality_controlled":0,"extern":1,"citation":{"mla":"Doyen, Laurent, et al. <i>Interface Theories with Component Reuse</i>. ACM, 2008, pp. 79–88, doi:<a href=\"https://doi.org/10.1145/1450058.1450070\">10.1145/1450058.1450070</a>.","apa":"Doyen, L., Henzinger, T. A., Jobstmann, B., &#38; Petrov, T. (2008). Interface theories with component reuse (pp. 79–88). Presented at the EMSOFT: Embedded Software , ACM. <a href=\"https://doi.org/10.1145/1450058.1450070\">https://doi.org/10.1145/1450058.1450070</a>","chicago":"Doyen, Laurent, Thomas A Henzinger, Barbara Jobstmann, and Tatjana Petrov. “Interface Theories with Component Reuse,” 79–88. ACM, 2008. <a href=\"https://doi.org/10.1145/1450058.1450070\">https://doi.org/10.1145/1450058.1450070</a>.","ama":"Doyen L, Henzinger TA, Jobstmann B, Petrov T. Interface theories with component reuse. In: ACM; 2008:79-88. doi:<a href=\"https://doi.org/10.1145/1450058.1450070\">10.1145/1450058.1450070</a>","short":"L. Doyen, T.A. Henzinger, B. Jobstmann, T. Petrov, in:, ACM, 2008, pp. 79–88.","ista":"Doyen L, Henzinger TA, Jobstmann B, Petrov T. 2008. Interface theories with component reuse. EMSOFT: Embedded Software , 79–88.","ieee":"L. Doyen, T. A. Henzinger, B. Jobstmann, and T. Petrov, “Interface theories with component reuse,” presented at the EMSOFT: Embedded Software , 2008, pp. 79–88."},"type":"conference","abstract":[{"lang":"eng","text":"Interface theories have been proposed to support incremental design and independent implementability. Incremental design means that the compatibility checking of interfaces can proceed for partial system descriptions, without knowing the interfaces of all components. Independent implementability means that compatible interfaces can be refined separately, maintaining compatibility. We show that these interface theories provide no formal support for component reuse, meaning that the same component cannot be used to implement several different interfaces in a design. We add a new operation to interface theories in order to support such reuse. For example, different interfaces for the same component may refer to different aspects such as functionality, timing, and power consumption. We give both stateless and stateful examples for interface theories with component reuse. To illustrate component reuse in interface-based design, we show how the stateful theory provides a natural framework for specifying and refining PCI bus clients."}],"year":"2008","page":"79 - 88","conference":{"name":"EMSOFT: Embedded Software "},"publist_id":"193","date_updated":"2021-01-12T07:59:30Z","author":[{"full_name":"Doyen, Laurent","last_name":"Doyen","first_name":"Laurent"},{"full_name":"Thomas Henzinger","first_name":"Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","last_name":"Henzinger","orcid":"0000−0002−2985−7724"},{"first_name":"Barbara","last_name":"Jobstmann","full_name":"Jobstmann, Barbara"},{"full_name":"Tatjana Petrov","first_name":"Tatjana","id":"3D5811FC-F248-11E8-B48F-1D18A9856A87","last_name":"Petrov","orcid":"0000-0002-9041-0905"}],"title":"Interface theories with component reuse","month":"10","date_published":"2008-10-01T00:00:00Z","publisher":"ACM"},{"publication":"Information Processing Letters","doi":"10.1016/j.ipl.2007.08.035","publication_status":"published","main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/reduction_of_stochastic_parity_to_stochastic_mean-payoff_games.pdf"}],"day":"31","quality_controlled":0,"status":"public","_id":"4534","date_created":"2018-12-11T12:09:21Z","abstract":[{"lang":"eng","text":"A stochastic graph game is played by two players on a game graph with probabilistic transitions. We consider stochastic graph games with ω-regular winning conditions specified as parity objectives, and mean-payoff (or limit-average) objectives. These games lie in NP ∩ coNP. We present a polynomial-time Turing reduction of stochastic parity games to stochastic mean-payoff games."}],"type":"journal_article","volume":106,"extern":1,"citation":{"chicago":"Chatterjee, Krishnendu, and Thomas A Henzinger. “Reduction of Stochastic Parity to Stochastic Mean-Payoff Games.” <i>Information Processing Letters</i>. Elsevier, 2008. <a href=\"https://doi.org/10.1016/j.ipl.2007.08.035\">https://doi.org/10.1016/j.ipl.2007.08.035</a>.","short":"K. Chatterjee, T.A. Henzinger, Information Processing Letters 106 (2008) 1–7.","ieee":"K. Chatterjee and T. A. Henzinger, “Reduction of stochastic parity to stochastic mean-payoff games,” <i>Information Processing Letters</i>, vol. 106, no. 1. Elsevier, pp. 1–7, 2008.","ista":"Chatterjee K, Henzinger TA. 2008. Reduction of stochastic parity to stochastic mean-payoff games. Information Processing Letters. 106(1), 1–7.","ama":"Chatterjee K, Henzinger TA. Reduction of stochastic parity to stochastic mean-payoff games. <i>Information Processing Letters</i>. 2008;106(1):1-7. doi:<a href=\"https://doi.org/10.1016/j.ipl.2007.08.035\">10.1016/j.ipl.2007.08.035</a>","mla":"Chatterjee, Krishnendu, and Thomas A. Henzinger. “Reduction of Stochastic Parity to Stochastic Mean-Payoff Games.” <i>Information Processing Letters</i>, vol. 106, no. 1, Elsevier, 2008, pp. 1–7, doi:<a href=\"https://doi.org/10.1016/j.ipl.2007.08.035\">10.1016/j.ipl.2007.08.035</a>.","apa":"Chatterjee, K., &#38; Henzinger, T. A. (2008). Reduction of stochastic parity to stochastic mean-payoff games. <i>Information Processing Letters</i>. Elsevier. <a href=\"https://doi.org/10.1016/j.ipl.2007.08.035\">https://doi.org/10.1016/j.ipl.2007.08.035</a>"},"year":"2008","publist_id":"188","page":"1 - 7","title":"Reduction of stochastic parity to stochastic mean-payoff games","author":[{"last_name":"Chatterjee","orcid":"0000-0002-4561-241X","first_name":"Krishnendu","id":"2E5DCA20-F248-11E8-B48F-1D18A9856A87","full_name":"Krishnendu Chatterjee"},{"id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","last_name":"Henzinger","orcid":"0000−0002−2985−7724","full_name":"Thomas Henzinger"}],"issue":"1","date_updated":"2021-01-12T07:59:30Z","publisher":"Elsevier","date_published":"2008-03-31T00:00:00Z","intvolume":"       106","month":"03"},{"publisher":"IEEE","month":"01","date_published":"2008-01-01T00:00:00Z","author":[{"last_name":"Chatterjee","orcid":"0000-0002-4561-241X","id":"2E5DCA20-F248-11E8-B48F-1D18A9856A87","first_name":"Krishnendu","full_name":"Krishnendu Chatterjee"},{"first_name":"Arkadeb","last_name":"Ghosal","full_name":"Ghosal, Arkadeb"},{"id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A","last_name":"Henzinger","orcid":"0000−0002−2985−7724","full_name":"Thomas Henzinger"},{"first_name":"Daniel","last_name":"Iercan","full_name":"Iercan, Daniel"},{"last_name":"Kirsch","first_name":"Christoph","full_name":"Kirsch, Christoph M"},{"last_name":"Pinello","first_name":"Claudio","full_name":"Pinello, Claudio"},{"full_name":"Sangiovanni-Vincentelli, Alberto","last_name":"Sangiovanni Vincentelli","first_name":"Alberto"}],"title":"Logical reliability of interacting real-time tasks","date_updated":"2021-01-12T07:59:36Z","publist_id":"171","conference":{"name":"DATE: Design, Automation and Test in Europe"},"page":"909 - 914","year":"2008","type":"conference","abstract":[{"lang":"eng","text":"We propose the notion of logical reliability for real-time program tasks that interact through periodically updated program variables. We describe a reliability analysis that checks if the given short-term (e.g., single-period) reliability of a program variable update in an implementation is sufficient to meet the logical reliability requirement (of the program variable) in the long run. We then present a notion of design by refinement where a task can be refined by another task that writes to program variables with less logical reliability. The resulting analysis can be combined with an incremental schedulability analysis for interacting real-time tasks proposed earlier for the Hierarchical Timing Language (HTL), a coordination language for distributed real-time systems. We implemented a logical-reliability-enhanced prototype of the compiler and runtime infrastructure for HTL."}],"citation":{"apa":"Chatterjee, K., Ghosal, A., Henzinger, T. A., Iercan, D., Kirsch, C., Pinello, C., &#38; Sangiovanni Vincentelli, A. (2008). Logical reliability of interacting real-time tasks (pp. 909–914). Presented at the DATE: Design, Automation and Test in Europe, IEEE. <a href=\"https://doi.org/10.1145/1403375.1403595\">https://doi.org/10.1145/1403375.1403595</a>","mla":"Chatterjee, Krishnendu, et al. <i>Logical Reliability of Interacting Real-Time Tasks</i>. IEEE, 2008, pp. 909–14, doi:<a href=\"https://doi.org/10.1145/1403375.1403595\">10.1145/1403375.1403595</a>.","ista":"Chatterjee K, Ghosal A, Henzinger TA, Iercan D, Kirsch C, Pinello C, Sangiovanni Vincentelli A. 2008. Logical reliability of interacting real-time tasks. DATE: Design, Automation and Test in Europe, 909–914.","ieee":"K. Chatterjee <i>et al.</i>, “Logical reliability of interacting real-time tasks,” presented at the DATE: Design, Automation and Test in Europe, 2008, pp. 909–914.","short":"K. Chatterjee, A. Ghosal, T.A. Henzinger, D. Iercan, C. Kirsch, C. Pinello, A. Sangiovanni Vincentelli, in:, IEEE, 2008, pp. 909–914.","ama":"Chatterjee K, Ghosal A, Henzinger TA, et al. Logical reliability of interacting real-time tasks. In: IEEE; 2008:909-914. doi:<a href=\"https://doi.org/10.1145/1403375.1403595\">10.1145/1403375.1403595</a>","chicago":"Chatterjee, Krishnendu, Arkadeb Ghosal, Thomas A Henzinger, Daniel Iercan, Christoph Kirsch, Claudio Pinello, and Alberto Sangiovanni Vincentelli. “Logical Reliability of Interacting Real-Time Tasks,” 909–14. IEEE, 2008. <a href=\"https://doi.org/10.1145/1403375.1403595\">https://doi.org/10.1145/1403375.1403595</a>."},"extern":1,"quality_controlled":0,"status":"public","day":"01","_id":"4546","date_created":"2018-12-11T12:09:25Z","publication_status":"published","main_file_link":[{"open_access":"0","url":"http://pub.ist.ac.at/%7Etah/Publications/logical_reliability_of_interacting_real-time_tasks.pdf"}],"doi":"10.1145/1403375.1403595"},{"year":"2008","publist_id":"168","page":"219 - 234","issue":"2","title":"Stochastic limit-average games are in EXPTIME","author":[{"last_name":"Chatterjee","orcid":"0000-0002-4561-241X","first_name":"Krishnendu","id":"2E5DCA20-F248-11E8-B48F-1D18A9856A87","full_name":"Krishnendu Chatterjee"},{"full_name":"Majumdar, Ritankar S","last_name":"Majumdar","first_name":"Ritankar"},{"full_name":"Thomas Henzinger","last_name":"Henzinger","orcid":"0000−0002−2985−7724","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","first_name":"Thomas A"}],"date_updated":"2021-01-12T07:59:37Z","publisher":"Springer","month":"01","intvolume":"        37","date_published":"2008-01-01T00:00:00Z","main_file_link":[{"url":"http://pub.ist.ac.at/%7Etah/Publications/stochastic_limit-average_games_are_in_exptime.pdf","open_access":"0"}],"doi":"10.1007/s00182-007-0110-5","publication_status":"published","publication":"International Journal of Game Theory","quality_controlled":0,"status":"public","day":"01","_id":"4548","date_created":"2018-12-11T12:09:25Z","type":"journal_article","abstract":[{"text":"The value of a finite-state two-player zero-sum stochastic game with limit-average payoff can be approximated to within ε in time exponential in a polynomial in the size of the game times polynomial in logarithmic in 1/ε, for all ε &gt; 0.","lang":"eng"}],"extern":1,"citation":{"apa":"Chatterjee, K., Majumdar, R., &#38; Henzinger, T. A. (2008). Stochastic limit-average games are in EXPTIME. <i>International Journal of Game Theory</i>. Springer. <a href=\"https://doi.org/10.1007/s00182-007-0110-5\">https://doi.org/10.1007/s00182-007-0110-5</a>","mla":"Chatterjee, Krishnendu, et al. “Stochastic Limit-Average Games Are in EXPTIME.” <i>International Journal of Game Theory</i>, vol. 37, no. 2, Springer, 2008, pp. 219–34, doi:<a href=\"https://doi.org/10.1007/s00182-007-0110-5\">10.1007/s00182-007-0110-5</a>.","ama":"Chatterjee K, Majumdar R, Henzinger TA. Stochastic limit-average games are in EXPTIME. <i>International Journal of Game Theory</i>. 2008;37(2):219-234. doi:<a href=\"https://doi.org/10.1007/s00182-007-0110-5\">10.1007/s00182-007-0110-5</a>","ieee":"K. Chatterjee, R. Majumdar, and T. A. Henzinger, “Stochastic limit-average games are in EXPTIME,” <i>International Journal of Game Theory</i>, vol. 37, no. 2. Springer, pp. 219–234, 2008.","ista":"Chatterjee K, Majumdar R, Henzinger TA. 2008. Stochastic limit-average games are in EXPTIME. International Journal of Game Theory. 37(2), 219–234.","short":"K. Chatterjee, R. Majumdar, T.A. Henzinger, International Journal of Game Theory 37 (2008) 219–234.","chicago":"Chatterjee, Krishnendu, Ritankar Majumdar, and Thomas A Henzinger. “Stochastic Limit-Average Games Are in EXPTIME.” <i>International Journal of Game Theory</i>. Springer, 2008. <a href=\"https://doi.org/10.1007/s00182-007-0110-5\">https://doi.org/10.1007/s00182-007-0110-5</a>."},"volume":37},{"date_published":"2007-01-01T00:00:00Z","intvolume":"         1","month":"01","publisher":"CSAV","date_updated":"2021-01-12T06:57:34Z","title":"Auxin - Universal development signal in plant life","author":[{"full_name":"Friml, Jirí","last_name":"Friml","orcid":"0000-0002-8302-7596","id":"4159519E-F248-11E8-B48F-1D18A9856A87","first_name":"Jirí"}],"user_id":"3E5EF7F0-F248-11E8-B48F-1D18A9856A87","publist_id":"4452","language":[{"iso":"cze"}],"year":"2007","volume":1,"citation":{"chicago":"Friml, Jiří. “Auxin - Universal development signal in plant life.” <i>Živa</i>. CSAV, 2007.","ieee":"J. Friml, “Auxin - Universal development signal in plant life,” <i>Živa</i>, vol. 1. CSAV, 2007.","ista":"Friml J. 2007. Auxin - Universal development signal in plant life. Živa. 1.","short":"J. Friml, Živa 1 (2007).","ama":"Friml J. Auxin - Universal development signal in plant life. <i>Živa</i>. 2007;1.","mla":"Friml, Jiří. “Auxin - Universal development signal in plant life.” <i>Živa</i>, vol. 1, CSAV, 2007.","apa":"Friml, J. (2007). Auxin - Universal development signal in plant life. <i>Živa</i>. CSAV."},"extern":"1","abstract":[{"text":"Signal molecules known as phytohormones play a decisive role in processing signals coming to plants from the surrounding environment. They include auxin — a simple compound with a large range of effects. Auxin is irregularly deposited in plant tissues, it accumulates in certain cellules and through activation of a signal cascade it causes changes in the development programme of these cellules. This article forms a part of the series prepared in honour of the anniversary of the important plant physiologist — Bohumil Němec.","lang":"eng"}],"type":"journal_article","date_created":"2018-12-11T11:57:44Z","_id":"2451","status":"public","day":"01","quality_controlled":"1","publication":"Živa","publication_status":"published","oa_version":"None"},{"doi":"10.1199/tab.0108","publication_status":"published","publication":"The Arabidopsis Book","_id":"2462","date_created":"2018-12-11T11:57:48Z","quality_controlled":0,"status":"public","day":"21","extern":1,"citation":{"chicago":"Michniewicz, Marta, Philip Brewer, and Jiří Friml. “Polar Auxin Transport and Asymmetric Auxin Distribution.” <i>The Arabidopsis Book</i>. The American Society of Plant Biologists, 2007. <a href=\"https://doi.org/10.1199/tab.0108\">https://doi.org/10.1199/tab.0108</a>.","ama":"Michniewicz M, Brewer P, Friml J. Polar auxin transport and asymmetric auxin distribution. <i>The Arabidopsis Book</i>. 2007;5. doi:<a href=\"https://doi.org/10.1199/tab.0108\">10.1199/tab.0108</a>","short":"M. Michniewicz, P. Brewer, J. Friml, The Arabidopsis Book 5 (2007).","ista":"Michniewicz M, Brewer P, Friml J. 2007. Polar auxin transport and asymmetric auxin distribution. The Arabidopsis Book. 5.","ieee":"M. Michniewicz, P. Brewer, and J. Friml, “Polar auxin transport and asymmetric auxin distribution,” <i>The Arabidopsis Book</i>, vol. 5. The American Society of Plant Biologists, 2007.","mla":"Michniewicz, Marta, et al. “Polar Auxin Transport and Asymmetric Auxin Distribution.” <i>The Arabidopsis Book</i>, vol. 5, The American Society of Plant Biologists, 2007, doi:<a href=\"https://doi.org/10.1199/tab.0108\">10.1199/tab.0108</a>.","apa":"Michniewicz, M., Brewer, P., &#38; Friml, J. (2007). Polar auxin transport and asymmetric auxin distribution. <i>The Arabidopsis Book</i>. The American Society of Plant Biologists. <a href=\"https://doi.org/10.1199/tab.0108\">https://doi.org/10.1199/tab.0108</a>"},"volume":5,"type":"journal_article","year":"2007","publist_id":"4441","date_updated":"2021-01-12T06:57:38Z","author":[{"full_name":"Michniewicz, Marta","last_name":"Michniewicz","first_name":"Marta"},{"first_name":"Philip","last_name":"Brewer","full_name":"Brewer, Philip B"},{"id":"4159519E-F248-11E8-B48F-1D18A9856A87","first_name":"Jirí","orcid":"0000-0002-8302-7596","last_name":"Friml","full_name":"Jirí Friml"}],"title":"Polar auxin transport and asymmetric auxin distribution","intvolume":"         5","month":"08","date_published":"2007-08-21T00:00:00Z","publisher":"The American Society of Plant Biologists"},{"date_updated":"2021-01-12T06:57:49Z","title":"Metabotropic glutamate receptor 4-immunopositive terminals of medium-sized spiny neurons selectively form synapses with cholinergic interneurons in the rat neostriatum","author":[{"full_name":"Kuramoto, Eriko","last_name":"Kuramoto","first_name":"Eriko"},{"last_name":"Fujiyama","first_name":"Fumino","full_name":"Fujiyama, Fumino"},{"full_name":"Unzai, Tomo","first_name":"Tomo","last_name":"Unzai"},{"first_name":"Kouichi","last_name":"Nakamura","full_name":"Nakamura, Kouichi"},{"last_name":"Hioki","first_name":"Hiroyuki","full_name":"Hioki, Hiroyuki"},{"full_name":"Furuta, Takahiro","last_name":"Furuta","first_name":"Takahiro"},{"orcid":"0000-0001-8761-9444","last_name":"Shigemoto","id":"499F3ABC-F248-11E8-B48F-1D18A9856A87","first_name":"Ryuichi","full_name":"Ryuichi Shigemoto"},{"full_name":"Ferraguti, Francesco","first_name":"Francesco","last_name":"Ferraguti"},{"last_name":"Kaneko","first_name":"Takeshi","full_name":"Kaneko, Takeshi"}],"issue":"5","date_published":"2007-02-10T00:00:00Z","intvolume":"       500","month":"02","publisher":"Wiley-Blackwell","year":"2007","page":"908 - 922","publist_id":"4406","date_created":"2018-12-11T11:58:00Z","_id":"2495","quality_controlled":0,"status":"public","day":"10","volume":500,"citation":{"apa":"Kuramoto, E., Fujiyama, F., Unzai, T., Nakamura, K., Hioki, H., Furuta, T., … Kaneko, T. (2007). Metabotropic glutamate receptor 4-immunopositive terminals of medium-sized spiny neurons selectively form synapses with cholinergic interneurons in the rat neostriatum. <i>Journal of Comparative Neurology</i>. Wiley-Blackwell. <a href=\"https://doi.org/10.1002/cne.21216\">https://doi.org/10.1002/cne.21216</a>","mla":"Kuramoto, Eriko, et al. “Metabotropic Glutamate Receptor 4-Immunopositive Terminals of Medium-Sized Spiny Neurons Selectively Form Synapses with Cholinergic Interneurons in the Rat Neostriatum.” <i>Journal of Comparative Neurology</i>, vol. 500, no. 5, Wiley-Blackwell, 2007, pp. 908–22, doi:<a href=\"https://doi.org/10.1002/cne.21216\">10.1002/cne.21216</a>.","ista":"Kuramoto E, Fujiyama F, Unzai T, Nakamura K, Hioki H, Furuta T, Shigemoto R, Ferraguti F, Kaneko T. 2007. Metabotropic glutamate receptor 4-immunopositive terminals of medium-sized spiny neurons selectively form synapses with cholinergic interneurons in the rat neostriatum. Journal of Comparative Neurology. 500(5), 908–922.","short":"E. Kuramoto, F. Fujiyama, T. Unzai, K. Nakamura, H. Hioki, T. Furuta, R. Shigemoto, F. Ferraguti, T. Kaneko, Journal of Comparative Neurology 500 (2007) 908–922.","ieee":"E. Kuramoto <i>et al.</i>, “Metabotropic glutamate receptor 4-immunopositive terminals of medium-sized spiny neurons selectively form synapses with cholinergic interneurons in the rat neostriatum,” <i>Journal of Comparative Neurology</i>, vol. 500, no. 5. Wiley-Blackwell, pp. 908–922, 2007.","ama":"Kuramoto E, Fujiyama F, Unzai T, et al. Metabotropic glutamate receptor 4-immunopositive terminals of medium-sized spiny neurons selectively form synapses with cholinergic interneurons in the rat neostriatum. <i>Journal of Comparative Neurology</i>. 2007;500(5):908-922. doi:<a href=\"https://doi.org/10.1002/cne.21216\">10.1002/cne.21216</a>","chicago":"Kuramoto, Eriko, Fumino Fujiyama, Tomo Unzai, Kouichi Nakamura, Hiroyuki Hioki, Takahiro Furuta, Ryuichi Shigemoto, Francesco Ferraguti, and Takeshi Kaneko. “Metabotropic Glutamate Receptor 4-Immunopositive Terminals of Medium-Sized Spiny Neurons Selectively Form Synapses with Cholinergic Interneurons in the Rat Neostriatum.” <i>Journal of Comparative Neurology</i>. Wiley-Blackwell, 2007. <a href=\"https://doi.org/10.1002/cne.21216\">https://doi.org/10.1002/cne.21216</a>."},"extern":1,"abstract":[{"text":"Metabotropic glutamate receptor 4 (mGluR4) is localized mainly to presynaptic membranes in the brain. Rat neostriatum has been reported to contain two types of mGluR4-immunoreactive axon varicosities: small, weakly immunoreactive varicosities that were distributed randomly (type 1) and large, intensely immunoreactive ones that were often aligned linearly (type 2). In the present study, most type 1 terminals formed asymmetric synapses on dendritic spines, whereas type 2 terminals made symmetric synapses on dendritic shafts, showing immunoreactivity for GABAergic markers. After depletion of neostriatal neurons, type 2 but not type 1 varicosities were largely decreased in the damaged region. When medium-sized spiny neurons (MSNs) were labeled with Sindbis virus expressing membrane-targeted green fluorescent protein, mGluR4 immunoreactivity was observed on some varicosities of their axon collaterals in immunofluorescence and immunoelectron microscopies. Furthermore, type 2 varicosities were often positive for substance P but mostly negative for striatal interneuron markers and preproenkephalin. Thus, striatonigral/striato- entopeduncular MSNs are likely to be the largest source of type 2 mGluR4-immunopositive axon terminals in the neostriatum. Next, in the double-immunofluorescence study, almost all choline acetyltransferase (ChAT)-immunopositive and 41% of NK1 receptor-positive dendrites were heavily associated with type 2 mGluR4-immunoreactive varicosities. Neuronal nitric oxide synthase (nNOS)-positive dendrites, in contrast, seemed associated with only a few type 2 varicosities. Conversely, almost all type 2 varicosities were closely apposed to NK1 receptor-positive dendrites that were known to be derived from cholinergic and nNOS-producing interneurons. These findings indicate that the mGluR4-positive terminals of MSN axon collaterals selectively form synapses with neostriatal cholinergic interneurons.","lang":"eng"}],"type":"journal_article","publication":"Journal of Comparative Neurology","doi":"10.1002/cne.21216","publication_status":"published"}]