DOI,IST REx ID,Research Group,Title of publication
10.4230/LIPIcs.CONCUR.2023.21,14405,ToHe,Hypernode automata
10.1007/978-3-030-94583-1_1,10774,ToHe,Flavors of sequential information flow
10.1007/978-3-030-99429-7_1,11355,ToHe,Information-flow interfaces
10.1007/s10009-020-00582-z,10861,ToHe,AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic
10.1007/978-3-030-29662-9_4,7232,ToHe,Mixed-time signal temporal logic
10.1145/3302504.3311800,6428,ToHe,Interface-aware signal temporal logic
10.1007/978-3-319-89963-3_18,299,ToHe,AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic
10.15479/AT:IST-2014-148-v2-1,5411,ToHe,Compositional specifications for IOCO testing
10.1007/978-3-642-34059-8_20,2942,ToHe,Independent implementability of viewpoints
10.1007/978-3-642-30793-5_13,3155,ToHe,Synchronous interface theories and time triggered scheduling
10.1007/978-3-642-29860-8_12,3162,ToHe,Parametric identification of temporal properties
10.1007/978-3-642-23217-6_27,3362,ToHe,Dynamic reactive modules
10.1007/978-3-642-15297-9_13,4369,ToHe,From MTL to deterministic timed automata
10.1007/s10703-009-0085-x,4379,,Analog property checkers: a DDR2 case study
10.1109/ACSD.2010.26,4389,ToHe,Robustness of sequential circuits
10.1007/978-3-540-78127-1_26,4371,,"Checking Temporal Properties of Discrete, Timed and Continuous Behaviors"
1567,4368,,AMT: a property-based monitoring tool for analog systems
1568,4370,,On synthesizing controllers from bounded-response properties
1571,4373,,"Real Time Temporal Logic: Past, Present, Future"
1570,4374,,From MITL to Timed Automata