@inproceedings{4608,
  abstract     = {State space explosion is a fundamental obstacle in formal verification of designs and protocols. Several techniques for combating this problem have emerged in the past few years, among which two are significant: partial-order reductions and symbolic state space search. In asynchronous systems, interleavings of independent concurrent events are equivalent, and only a representative interleaving needs to be explored to verify local properties. Partial-order methods exploit this redundancy and visit only a subset of the reachable states. Symbolic techniques, on the other hand, capture the transition relation of a system and the set of reachable states as boolean functions. In many cases, these functions can be represented compactly using binary decision diagrams (BDDs). Traditionally, the two techniques have been practiced by two different schools—partial-order methods with enumerative depth-first search for the analysis of asynchronous network protocols, and symbolic breadth-first search for the analysis of synchronous hardware designs. We combine both approaches and develop a method for using partial-order reduction techniques in symbolic BDD-based invariant checking. We present theoretical results to prove the correctness of the method, and experimental results to demonstrate its efficacy.},
  author       = {Alur, Rajeev and Brayton, Robert and Henzinger, Thomas A and Qadeer, Shaz and Rajamani, Sriram},
  booktitle    = {9th International Conference on Computer Aided Verification},
  isbn         = {9783540631668},
  location     = {Haifa, Israel},
  pages        = {340 -- 351},
  publisher    = {Springer},
  title        = {{Partial-order reduction in symbolic state-space exploration}},
  doi          = {10.1007/3-540-63166-6_34},
  volume       = {1254},
  year         = {1997},
}

@inproceedings{4494,
  abstract     = {A hybrid system consists of a collection of digital programs that interact with each other and with an analog environment. Examples of hybrid systems include medical equipment, manufacturing controllers, automotive controllers, and robots. The formal analysis of the mixed digital-analog nature of these systems requires a model that incorporates the discrete behavior of computer programs with the continuous behavior of environment variables, such as temperature and pressure. Hybrid automata capture both types of behavior by combining finite automata with differential inclusions (i.e. differential inequalities). HyTech is a symbolic model checker for linear hybrid automata, an expressive, yet automatically analyzable, subclass of hybrid automata. A key feature of HyTech is its ability to perform parametric analysis, i.e. to determine the values of design parameters for which a linear hybrid automaton satisfies a temporal requirement.},
  author       = {Henzinger, Thomas A and Ho, Pei and Wong Toi, Howard},
  isbn         = {9783540631668},
  location     = {Haifa, Israel},
  pages        = {460 -- 463},
  publisher    = {Springer},
  title        = {{HyTech: A model checker for hybrid systems}},
  doi          = {10.1007/3-540-63166-6_48},
  volume       = {1254},
  year         = {1997},
}